1. Field of the Invention
The present invention relates to a semiconductor power device, and particularly to an Insulated Gate Bipolar Transistor (hereinafter, referred to as an IGBT) being a MOS Bipolar composite functional device capable of performing high-speed operations in a medium electric power area of breakdown voltage 1200 V or more.
2. Description of the Prior Art
Lately, MOS composite devices such as an IGBT, a MOS Controlled Thyristor (MCT), an Emitter Switched Thyristor (EST), or the like have been developed. Since these are voltage-driving power devices and easy to use, requirements for developing these new MOS composite devices have fairly been made from a system operation side and its development has abruptly been advanced in response thereto.
The IGBT is a transistor having a unit cell cross-sectional structure as represented in FIG. 13, and has a composite structure provided with a MOSFET structure in its upper part and a bipolar transistor structure in its lower part. This structure and basic operations are disclosed in the Japanese Patent Application Laid Open No. 57-120369 Official Gazette. On the basis of this description, a conventional N-channel IGBT will be explained. In FIG. 13, a high-resistivity N.sup.- base region 2 having low impurity concentration is formed in a P-type collector region 1. On the surface of the N.sup.- base region 2, a P-type base region 3 is formed by a Double Diffusion Self Alignment method so as to expose its surface. Furthermore, an N.sup.+ emitter region 4 is formed in the P-type base region 3 so as to expose its surface. On the surface of the P-type base region 3, a polysilicon gate electrode 6 is provided on a thin insulation film 5 such as SiO.sub.2 etc. This gate electrode 6 overlaps the P-type base region 3 and is disposed so as to cover from the N.sup.- base region 2 to the N.sup.+ emitter region 4. A metal emitter electrode 7 is provided so that the N.sup.+ emitter region 4 may be short-circuited with the P-type base region 3, and a metal gate 8 connecting to the polysilicon gate electrode 6 and a metal collector electrode 9 connecting to the P-type collector region 1 are provided, respectively. Also, in a structure as depicted in FIG. 14, an N.sup.+ buffer region 20 is provided between the P-type collector region 1 and N.sup.- base region 2 and such IGBT has generally been known. A general method of manufacturing these conventional N-channel IGBTs will be described below. First, the P-type silicon semiconductor substrate 1 having a thickness of about 150 .mu.m and impurity concentration of about 10.sup.18 to 10.sup.20 cm.sup.-3 is used as a P-type collector region. A semiconductor layer 2 is formed in vapor-phase epitaxy on this semiconductor substrate 1 to act as the N.sup.- base region. In the embodiment of FIG. 14, after a semiconductor layer 20 being an N.sup.+ buffer region has formed in vapor-phase epitaxy, the semiconductor layer 2 will be formed. Thus, a P-N.sup.- (or P-N-N.sup.-) wafer is formed. Next, the insulation film 5 such as SiO.sub.2 etc. is formed on the surface of the N.sup.- base region 2, and further the polysilicon gate electrode 6 is formed thereon. Next, the polysilicon gate electrode 6 and insulation film 5 are partially opened, and with the use of the polysilicon electrode 6 as a mask, the P-type base region 3 is formed, and further two N.sup.+ emitter regions 4 are formed within the P-type base region 3. Next, the insulation film 5 is formed again on the polysilicon gate electrode 6 and P-type base region 3, and further the insulation film 5 formed on the P-type base region 3 containing the polysilicon gate electrode 6 and N.sup.+ emitter region 4 is partially removed. Thereafter the window parts in the insulation film on the P-type base region 3, N.sup.+ emitter region 4 and the polysilicon gate electrode 6 are deposited with a metal such as aluminum etc. to form the metal gate electrode 8 and metal emitter electrode 7. Thereafter, the metal collector electrode 9 is formed in the P-type collector region 1 to obtain the conventional IGBT as shown in FIGS. 13, 14.
Next, an operation of the IGBT will be explained. The metal emitter electrode 7 is connected to the ground and a positive voltage for the metal emitter electrode 7 is applied to the metal gate electrode 8 in a condition that a positive voltage is applied to the metal collector electrode 9, whereby a turn-on of the IGBT can be realized. When a positive voltage is applied to the metal gate electrode 8, an inversion channel is formed on the surface of the P-type base region 8 in the same manner as the MOSFET and electrons flow into the inside of the N.sup.- base region 2 through the inversion channel from the N.sup.+ emitter region 4. As a result, holes occur to inject into N.sup.- base region 2 from the P-type collector region 1, and a PN junction between the P-type collector region 1 and the N.sup.- base region 2 or N-type buffer region 20 (in the embodiment of FIG. 14) becomes in a forward bias state, and the N.sup.- base region 2 causes a conductivity modulation so that the IGBT is guided into a conductive state. As described above, since the resistance in the high-resistivity N.sup.- base region 2 become extremely small due to the conductivity modulation, even if the element has lower concentration of the N.sup.- base region 2 and is thick with high breakdown voltage, a characteristic of extremely small on-resistance can be obtained by the IGBT. On the other hand, a negative voltage for the metal emitter electrode 7 is applied to the metal gate electrode 8, whereby a turn-off of the IGBT can be realized. When a negative voltage is applied to the metal gate electrode 8, the inversion channel is vanished and electrons stop flowing into the N.sup.- base region 2 from the N.sup.+ emitter region 4. However, electrons have existed as before within the N.sup.- base region 2. Most of the holes stored within the N.sup.- base region 2 pass through the P-type base region 3 and flow into the emitter electrode 7, however a part thereof is recombined with electrons existing within the N.sup.- base region 2 and disappears. At the time when all the holes stored within the N.sup.- base region 2 disappear, the IGBT becomes in a blocking state to complete the turn-off.
The high-voltage IGBT is an excellent element which is extremely low on-resistance, however there are some drawbacks that, since it is a minority carrier device, a turn-off time is elongated. A part of a minority carriers (holes) which are injected from a collector region to an N.sup.- base region is stored within the N.sup.- base region as excessive minority carriers. Accordingly, even if a gate voltage is reduced to zero in order to turn off this IGBT and the channel is closed to stop a flow of electrons, an off-state is not available until the stored minority carriers have been discharged. Furthermore, when the electrons existing in the N.sup.- base region 2 pass through the collector region at this turn-off time, new holes are induced to inject from the collector region to consequently elongate the turn-off time. Therefore, in the IGBT, a current can flow about 10 times as much as the normal MOSFET, however the IGBT has drawbacks that its turn-off time comes to elongate 10 times or more as much as the normal MOSFET. In the case where such IGBT is applied to, for instance, switching devices such as an inverter, since the turn-off time is elongated as described above, high switching frequency cannot be obtained, so that its application field is limited. As a method of improving the turn-off time of the IGBT, a method of shortening a carrier life time is generally adopted in the prior art. Specifically, a heavy metal diffusion method such as Au, Pt is taken, or the carrier life time is shortened by radioactive ray such as neutron rays, .gamma. rays or electron beams. Although the turn-off time is improved in this method, the degree of conduction modulation in the N.sup.- base region is simultaneously lowered and the low on-resistance characteristic which is the maximum advantage of the IGBT is deteriorated. Also, as another method, there is a method that the injection of holes from the P-type collector region is suppressed reducing the impurity concentration in the P-type collector region. With reference to FIG. 12, total impurity amount dependence in a collector region for a turn-off time of IGBT will be explained. The axis of ordinates denotes a turn-off time (.mu.s) and the axis of abscissas denotes total impurity dose Q.sub.D in the case where it is estimated per 1 cm.sup.2 of the entire area of a unit cell D in a collector region of IGBT. A curve as shown in this diagram is the characteristics of IGBT in which the collector region with a depth of 0.1 .mu.m is formed on the entire surface of a second main surface of a semiconductor substrate and further a carrier life time shortening is employed to obtain the turn-off time of 10 .mu.s. A numerical value Cs on the curve denotes impurity concentration in the collector region. Also, the total impurity dose in the collector region on the axis of abscissas is a vale when ions of .sup.11 B.sup.+ are implanted at 20 KeV through an oxide film having a film thickness 100 nm. From a viewpoint of FIG. 12, it is understood, as one method of improving the turn-off time, that it is necessary to reduce the impurity concentration in the collector region in order to suppress injection efficiency of holes from the collector region. However, when the impurity concentration in the P-type collector region is reduced, the contact resistance between the semiconductor collector region and metal collector electrode is increased and its amount of scatter are also extended, whereby this poor contact deteriorates the on-resistance characteristics of the IGBT. This is because the junction depth should be shallow, or 0.1 .mu.m, with such a low total impurity dose in collector region 1 of about 10.sup.12 to 10.sup.14 cm.sup.-2, to obtain high surface impurity concentration required to make a good ohmic contact. And if the junction depth is shallowed like this, the metal material of collector electrode penetrates through the collector region to produce a spike or a piping. Then, it is apprehensive that the N.sup.- base region is short-circuited and it is difficult to stably manufacture the device.
In addition, there is another method of increasing the impurity concentration of the N-type buffer region. However, since the controllability of the present vapor-phase epitaxy method is low, it is impossible to stably manufacture devices. Also, impurities in the N-type buffer region diffuse within the N.sup.- base region by thermal hysteresis in an IGBT manufacturing process, and finally the concentration off the N-type buffer region 20 is decreased and its thickness is increased, so that some problems occur that expected effects are not obtained. Furthermore, in the case of a high voltage IGBT having breakdown voltage BV.sub.CES 1200 V or more between the collector and emitter, a thick N.sup.- base region having very low concentration of 5.times.10.sup.13 atm/cm.sup.3 or less and a thickness of 100 .mu.m or more is required, and it is difficult to form such thick epitaxial layer or to stably manufacture devices by the present vapor-phase epitaxy. Also, in a structure as shown in FIG. 15, a double diffusion type DMOS structure is formed on one main surface of an N.sup.- semiconductor substrate having low concentration and the P-type collector region 1 is formed on the other main surface by implanting ions, and such structure has been disclosed in the Japanese Patent Application Laid Open No. 2-7569 Official Gazette. However, since, in such structure, the total impurity dose in the P-type collector region 1 per unit area is low, or about 10.sup.12 to 10.sup.14 cm.sup.-2, the junction must be shallowed, or 0.1 .mu.m to make an ohmic contact with the metal collector electrode 9, and then it is apprehensive that the metal collector electrode penetrate through the P.sup.+ collector region 1 and that the P.sup.+ collector region 1 is short-circuited with the N.sup.- base region 2, therefore there occur some problems that it is impossible to manufacture stably devices. Also, in the case where the junction is deep, or set at about 3 .mu.m, the surface concentration of the P.sup.+ collector region 1 becomes very low, or about 5.times.10.sup.15 to 1.times.10.sup.16 atm/cm.sup.3, therefore it becomes difficult to make an ohmic contact with the metal collector electrode 9, and as a result, there are drawbacks that the on-voltage of the IGBT becomes high.
And there is another IGBT called "the corrector-short IGBT" as shown in FIG. 16, the P-type collector region 1 is partially provided and the metal collector electrode 9 is formed so that the P-type collector region 1 may be short-circuited with the N.sup.- base region 2. In the embodiment of this structure, as a main current flows into a shunt resistor formed in a short part, there occur some problems that the on-resistance becomes high by the voltage drop caused by this.